The present invention provides permutation instructions which can be used in software executed in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. For fast cryptography, bit-level permutations are used, whereas for multimedia, permutations on subwords of typically 8 bits or 16 bits are used. Permutation instructions of the present invention can be used to provide any arbitrary permutation of sixty-four 1-bit subwords in a 64-bit processor, i.e., a processor with 64-bit words, registers and datapaths, for use in fast cryptography. The permutation instructions of the present invention can also be used for permuting subwords greater than 1 bit in size, for use in fast multimedia processing. For example, in addition to being able to permute sixty-four 1-bit subwords in a register, the permutation instructions and underlying functional unit can permute thirty-two 2-bit subwords, sixteen 4-bit subwords, eight 8-bit subwords, four 16-bit subwords, or two 32-bit subwords. The permutation instructions of the present invention can be added as new instructions to the Instruction Set Architecture of a conventional microprocessor, or they can be used in the design of new processors or coprocessors to be efficient for both cryptography and multimedia software.

A PPERM instruction is defined to perform permutations by a sequence of instructions with each sequence specifying the position in the source for each bit in the destination. In the PPERM instruction bits in the destination register that change are updated and bits in the destination register that do not change are set to zero. Alternatively, a PPERM3R instruction is defined to perform permutations. The PPERM3R instruction is similar to the PPERM instruction except that the bits from the destination register which do not change are copied unchanged, rather than set to zero as in PPERM. Accordingly, the PPERM3R instruction uses three source registers because the destination register is also a source register since the unchanged bits are held in the destination register. For every one of n bits to be changed in the final permutation, lgn bits can be used in the PPERM instruction or the PPERM3R instruction to specify which bit in the source register should replace the bit to be changed in the destination register.

In an alternate embodiment, a GRP instruction is defined to perform permutations. The GRP instruction divides the initial sequence in the source register into two groups depending on configuration bits. The first group is concatenated with the second group to form the result of one GRP instruction, which is also an intermediate bit sequence toward the final permutation. The total number of GRP instructions for a permutation of n bits is up to lgn.

In an embodiment of the present invention, multibit subwords are permuted with the GRP instruction. In a further embodiment of the invention, the method and system are scaled for performing permutations of 2n bits in which subwords are packed into two or more registers. In this embodiment, at most 2 lg n + 4 instructions are used to permute 2n bits using n-bit words.